This invention relates to reduction of transient noise in the output signal of the output buffer of digital integrated circuits. In particular, this invention relates to an improved output buffer circuit for an integrated circuit, including resistors for damping the transient noise in the output buffer circuits.
An EPROM array is one example of an integrated circuit in which the circuit and method of this invention may be used. EPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen row-line select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen row-line select voltage is applied to the control gate. The conductive state is read as a "one" bit. The output state of a cell is read by a sense amplifier, which transmits the data to a microprocessor by way of an output buffer circuit.
Certain prior-art output buffer circuits have had relatively large negative transient voltages (transient noise) during signal transitions, the transient voltages resulting from sudden decreases in current in the transistors of those output buffer circuits.
There is a need for reduction in the transient noise of digital-integrated-circuit output buffers, particularly during transitions of the input signals.